Mehdi Saligane's Homepage

Publications

Please also visit my Google Scholar page for an updated catalogue. This is a list of recent publications from my research:

2024

• A Li, J Lee, P Mukim, BD. Hoskins, P Shrestha, DD Wentzloff, D Blaauw, D Sylvester, M Saligane, A fully integrated, automatically generated DC-DC converter maintaining > 75% efficiency from 398 K down to 23 K across wide load ranges in 12 nm FinFET, IEEE Solid-State Circuits Letters (under review)

2023

• A Akturk, A Tripathi, M Saligane, Cryogenic Modeling for Open-Source Process Design Kit Technology, IEEE BCICTS
• A Hammoud, V Shankar, R Mains, J Matres, T Ansell, M Saligane, OpenFASOC: An Open Platform Towards Analog and Mixed-Signal Automation and Acceleration of Chip Design, 2023 International Symposium on Devices, Circuits and Systems (ISDCS) 1, 01-04
• YK Cherivirala, M Saligane, DD Wentzloff, An Open Source Compatible Framework to Fully Autonomous Digital LDO Generation, 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5
• A Li, W Zhang, M Saligane, SCS PICO Chronicles: A μProcessor With a 5-GHz Radio [Society News], IEEE Solid-State Circuits Magazine

2022

• Q Zhang, W Duan, T Edwards, T Ansell, D Blaauw, D Sylvester, M Saligane, An Open-Source and Autonomous Temperature Sensor Generator Verified With 64 Instances in SkyWater 130 nm for Comprehensive Design Space Exploration, IEEE Solid-State Circuits Letters
• M. Saligane, V-M Mirjana, to Support Open Source Ecosystem Ramp-Up, IEEE Solid-State Circuits Magazine

2021

• L Xu, J Lee, M Saligane, D Blaauw, D Sylvester, Design techniques of integrated power management circuits for low power edge devices, 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-4

2020

• J Lee, M Saligane, D Blaauw, D Sylvester, A 0.3-V to 1.8–3.3-V Leakage-Biased Synchronous Level Converter for ULP SoCs, SSCL
• T Ajayi, S Kamineni, M Fayazi, YK Cherivirala, K Kwon, S Gupta, W Duan, J Lee, C-H Chen, M Saligane, D Sylvester, D Blaauw, R Dreslinski Jr, B Calhoun, DD Wentzloff, Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation, VLSI-SoC
• T Ansell, M Saligane, The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts, ICCAD Invited Talk

Patents

• “DNA Synthesis, RNA Synthesis, and Cell Engineering On-A-Chip”, Submitted with Alea Biosciences Inc.
• “CPU performance monitor”, EU Patent with STMicroelectronics
• “Level Converter Circuitry”, Patent US 10,326,449 B2